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Soft Error Hardened Latch

Biol. (1956 - present) Phys. Mater. (2000 - 2015) Semicond. IEEE J. Int’l Conference on Dependable Systems and Networks (DSN), June 2002, pp. 389–399 (2002)6.Kastensmidt, F., Sterpone, L., Sonza Reorda, M., Carrro, L.: On the optimal design of triple modular redundancy logic for check over here

IBM J. B (2008 - present) Chinese Phys. on Computer-Aided Design of Integrated Circuits and Systems 27(10), 1788–1797 (2008)CrossRef16.Mitra, S., Seifert, N., Zhang, M., Shi, Q., Kim, K.S.: Robust system design with built-in soft-error resilience. Lett. (2006 - present) Eur. http://ieeexplore.ieee.org/iel5/5116585/5116586/05116607.pdf?arnumber=5116607

Lett. (1984 - present) Class. J. The system returned: (22) Invalid argument The remote host or network may be down.

  1. Oklobdzija (19) Author Affiliations 18.
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  5. JSAP is a "conduit" for the transfer of fundamental concepts to the industry for development and technological applications.JSAP was established as an official academic society in 1946, and since then, it
  6. Errors may be caused by a defect, usually understood either to be a mistake in design or construction, or a broken component.
  7. The key technology of the latch is a feedback loop circuit with a data node and four gates.
  8. Phys. (1962 - present) Laser Phys. (2013 - present) Laser Phys.
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Cosmol. Phys. Izv. J.

The law is named after Intel co-founder Gordon E. Fluoresc. (2013 - present) Metrologia (1965 - present) Modelling Simul. Meas. (1993 - present) Plasma Phys. (1967 - 1983) Plasma Phys. http://link.springer.com/chapter/10.1007%2F978-3-642-11802-9_30 Phys. (1982 - present) Comput.

on Device and Materials Reliability 8(1), 203–209 (2008)CrossRef19.Stackhouse, B., Bhimji, S., Bostak, C., Bradley, D., Cherkauer, B., Desai, J., Francom, E., Gowan, M., Gronowski, P., Krueger, D., Morganti, C., Troyer, S.: A USSR Izv. (1967 - 1992) Math. Please enable JavaScript to use all the features on this page. Technol. (1986 - present) Smart Mater.

J. Math. (1995 - present) Sci. Res. (1986 - present) IOP Conf. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Reader QuickTime Windows Media Player Real Player Did you know the ACM DL App is

Screen reader users, click the load entire article button to bypass dynamically loaded article content. check my blog Phys. (1968 - 1972) J. Struct. (1992 - present) Sov. Sci.

Nucl. Usp. (1958 - 1992) Supercond. Gen. (1973 - 1974) J. http://phabletkeyboards.com/soft-error/soft-error-ecc.php In addition, the latch protects from not only retention data upset but also transient noise releasing.

The ACM Guide to Computing Literature All Tags Export Formats Save to Binder SIGN IN SIGN UP Analysis and design of soft-error hardened latches Full Text: PDF Get Phys.: Condens. Technol. (1999 - present) Plasma Sources Sci.

Test Conference, November 2005, pp. 687–696 (2005)3.Omana, M., Rossi, D., Metra, C.: Latch susceptibility to transient faults and new hardening approach.

IET Computers & Digital Techniques 3(3), 289–303 (2009)CrossRef8.Karnik, T., Vangal, S., Veeramachaneni, V., Hazucha, P., Erraguntla, V., Borkar, S.: Selective node engineering for chip-level soft error rate improvement. That is, sequential logic has state (memory) while combinational logic does not. The HSPICE post-layout simulation in 90nm CMOS technology reveals that circuit is able to recover from almost any single particle strike on internal nodes and tolerates input SETs up to 130ps Nat.

Phys. Physiol. University of Texas at Dallas, Richardson, TX, 75080, USA Continue reading... have a peek at these guys Copyright © 2016 ACM, Inc.

Mol. B: Quantum Semiclass. We also discuss a method of soft error estimation in robust circuits in this paper. Springer, Heidelberg (2006)21.Oklobdzija, V.G., Stojanovic, V.M., Markovic, D.M., Nedovic, N.: Digital System Clocking: High Performance and Low-Power Aspects.

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