Download PDFs Help Help ERROR The requested URL could not be retrieved The following error was encountered while trying to retrieve the URL: http://0.0.0.5/ Connection to 0.0.0.5 failed. It is often used with stress testing and is widely considered to be an important part of developing robust software. Reliability Engineering is a sub-discipline within Systems Engineering. morefromWikipedia Single event upset A single event upset (SEU) is a change of state caused by ions or electro-magnetic radiation striking a sensitive node in a micro-electronic device, such as in http://dl.acm.org/citation.cfm?id=1046212
Hence, we propose a functional equivalent class based soft error mitigation scheme to exploit free LUT entries in the circuit. Generated Fri, 28 Oct 2016 01:09:36 GMT by s_wx1196 (squid/3.5.20) Full-text · Article · Jun 2011 Rawad Al-HaddadRashad OreifejRizwan AshrafRonald F.
See all ›46 CitationsSee all ›35 ReferencesShare Facebook Twitter Google+ LinkedIn Reddit Request full-text Soft error rate estimation and mitigation for SRAM-based FPGAsConference Paper · February 2005 with 25 ReadsDOI: 10.1145/1046192.1046212 · Source: DBLPConference: Proceedings Soft error rate (SER) estimation is a crucial step in the design of soft error tolerant schemes to balance reliability, performance, and cost of the system. Did you know your Organization can subscribe to the ACM Digital Library? Results from these irradiation experiments show that RO period variations, up to 6.2 ns for Virtex-5 and 3.8 ns for Artix-7, could be induced.
The proposed technique replaces not fully-occupied LUTs with corresponding functional equivalent classes, which can improve the reliability while preserve the functionality of the design. have a peek at these guys morefromWikipedia Tools and Resources Buy this Article Recommend the ACM DLto your organization Request Permissions TOC Service: Email RSS Save to Binder Export Formats: BibTeX EndNote ACMRef Upcoming Conference: FPGA '17 The failure rate of a system usually depends on time, with the rate varying over the life cycle of the system. Use of this web site signifies your agreement to the terms and conditions.
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Generated Fri, 28 Oct 2016 01:09:36 GMT by s_wx1196 (squid/3.5.20) ERROR The requested URL could not be retrieved The following error was encountered while trying to retrieve the URL: http://0.0.0.10/ Connection memory "bit"). For more information, visit the cookies page.Copyright © 2016 Elsevier B.V. The evaluation criterion of a design against soft errors is SER , which is computed as the probability of a fault occurs at it.
Screen reader users, click the load entire article button to bypass dynamically loaded article content. Publisher conditions are provided by RoMEO. A soft error is also a signal or datum which is wrong, but is not assumed to imply such a mistake or breakage. The system returned: (22) Invalid argument The remote host or network may be down.
SIGN IN SIGN UP Soft error rate estimation and mitigation for SRAM-based FPGAs Full Text: PDF Get this Article Authors: Ghazanfar Asadi Northeastern University, Boston, MA Mehdi B. Click the View full text link to bypass dynamically loaded article content. SistoL. The system returned: (22) Invalid argument The remote host or network may be down.
The hardware layer is implemented on a Xilinx Virtex-4 Field Programmable Gate Array (FPGA) to provide self-repair using a novel approach called reconfigurable adaptive redundancy system (RARS). Reliability is often measured as probability of failure, frequency of failures, or in terms of availability, a probability derived from reliability and maintainability. View full text Microelectronics ReliabilityVolume 50, Issue 8, August 2010, Pages 1171–1180 Two effective methods to mitigate soft error effects in SRAM-based FPGAsAlireza Rohani , Hamid R. Previous techniques on FPGA SER estimation are based on time-consuming fault injection and simulation methods.In this paper, we present an analytical approach to estimate the failure rate of designs mapped into
The logic resources utilize a new function generator that can tolerate 100% of single faults in its configuration memory while it can generate all the k-input Boolean functions.