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Soft Error Mitigation For Sram Based Fpgas

In this work, we observe that there are a lot of not-fully occupied look-up tables (LUTs) after logic synthesis. Your cache administrator is webmaster. JavaScript is disabled on your browser. ScienceDirect ® is a registered trademark of Elsevier B.V.RELX Group Recommended articles No articles found. weblink

Download PDFs Help Help ERROR The requested URL could not be retrieved The following error was encountered while trying to retrieve the URL: http://0.0.0.5/ Connection to 0.0.0.5 failed. It is often used with stress testing and is widely considered to be an important part of developing robust software. Reliability Engineering is a sub-discipline within Systems Engineering. morefromWikipedia Single event upset A single event upset (SEU) is a change of state caused by ions or electro-magnetic radiation striking a sensitive node in a micro-electronic device, such as in http://dl.acm.org/citation.cfm?id=1046212

Hence, we propose a functional equivalent class based soft error mitigation scheme to exploit free LUT entries in the circuit. Generated Fri, 28 Oct 2016 01:09:36 GMT by s_wx1196 (squid/3.5.20) Full-text · Article · Jun 2011 Rawad Al-HaddadRashad OreifejRizwan AshrafRonald F.

morefromWikipedia Application-specific integrated circuit An application-specific integrated circuit, or ASIC /¿e¿s¿k/, is an integrated circuit (IC) customized for a particular use, rather than intended for general-purpose use. This mitigates possible speed and density disadvantages that conventional FPGAs could have over ASICs and it translates into higher capability and speeds when compared to rad-hard FPGAs. "[Show abstract] [Hide abstract] Please note that Internet Explorer version 8.x will not be supported as of January 1, 2016. ElsevierAbout ScienceDirectRemote accessShopping cartContact and supportTerms and conditionsPrivacy policyCookies are used by this site.

GevinO. Please enable JavaScript to use all the features on this page. Please refer to this blog post for more information. https://www.researchgate.net/publication/221224583_Soft_error_rate_estimation_and_mitigation_for_SRAM-based_FPGAs In the interconnection resources, a kind of formation redundancy that can detect 94% of single faults in its configuration memory is applied.

This page uses JavaScript to progressively load the article content as a user scrolls. For example, a chip designed to run in a digital voice recorder is an ASIC. The software layer supervises the organic activities on the FPGA and extends the self-healing capabilities through application-independent, intrinsic, and evolutionary repair techniques that leverage the benefits of dynamic partial reconfiguration (PR). SMART was evaluated using a Sobel edge-detection application and was shown to tolerate stressful sequences of injected transient and permanent faults while reducing dynamic power consumption by 30% compared to conventional

See all ›46 CitationsSee all ›35 ReferencesShare Facebook Twitter Google+ LinkedIn Reddit Request full-text Soft error rate estimation and mitigation for SRAM-based FPGAsConference Paper · February 2005 with 25 ReadsDOI: 10.1145/1046192.1046212 · Source: DBLPConference: Proceedings Soft error rate (SER) estimation is a crucial step in the design of soft error tolerant schemes to balance reliability, performance, and cost of the system. Did you know your Organization can subscribe to the ACM Digital Library? Results from these irradiation experiments show that RO period variations, up to 6.2 ns for Virtex-5 and 3.8 ns for Artix-7, could be induced.

The proposed technique replaces not fully-occupied LUTs with corresponding functional equivalent classes, which can improve the reliability while preserve the functionality of the design. have a peek at these guys morefromWikipedia Tools and Resources Buy this Article Recommend the ACM DLto your organization Request Permissions TOC Service: Email RSS Save to Binder Export Formats: BibTeX EndNote ACMRef Upcoming Conference: FPGA '17 The failure rate of a system usually depends on time, with the rate varying over the life cycle of the system. Use of this web site signifies your agreement to the terms and conditions.

The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration, The fault injection experiments allow a better understanding of the behaviour of IOBs affected by additional delays due to configuration bit flips, which in many cases is similar to what can The results show that the area, power, and delay overheads are respectively 179%, 94%, and 60% in comparison with the simple architecture.Corresponding author.Copyright © 2010 Elsevier Ltd. check over here For full functionality of ResearchGate it is necessary to enable JavaScript.

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These results also reveal that the occurrence rate of events (namely delays and breaks) affecting ROs implemented in IOBs is approaching the rate observed when ROs are implemented in the FPGA

Generated Fri, 28 Oct 2016 01:09:36 GMT by s_wx1196 (squid/3.5.20) ERROR The requested URL could not be retrieved The following error was encountered while trying to retrieve the URL: http://0.0.0.10/ Connection memory "bit"). For more information, visit the cookies page.Copyright © 2016 Elsevier B.V. The evaluation criterion of a design against soft errors is SER [14], which is computed as the probability of a fault occurs at it.

After observing a soft error, there is no implication that the system is any less reliable than before. Full-text · Article · Sep 2014 Fatima Zahra TaziClaude ThibeaultYvon Savaria+1 more author ...Yves AudetRead full-textExploiting free LUT entries to mitigate soft errors in SRAM-based FPGAs"The first step of performing soft US & Canada: +1 800 678 4333 Worldwide: +1 732 981 0060 Contact & Support About IEEE Xplore Contact Us Help Terms of Use Nondiscrimination Policy Sitemap Privacy & Opting Out this content morefromWikipedia Fault injection In software testing, fault injection is a technique for improving the coverage of a test by introducing faults to test code paths, in particular error handling code paths,

Screen reader users, click the load entire article button to bypass dynamically loaded article content. Publisher conditions are provided by RoMEO. A soft error is also a signal or datum which is wrong, but is not assumed to imply such a mistake or breakage. The system returned: (22) Invalid argument The remote host or network may be down.

SIGN IN SIGN UP Soft error rate estimation and mitigation for SRAM-based FPGAs Full Text: PDF Get this Article Authors: Ghazanfar Asadi Northeastern University, Boston, MA Mehdi B. Click the View full text link to bypass dynamically loaded article content. SistoL. The system returned: (22) Invalid argument The remote host or network may be down.

The hardware layer is implemented on a Xilinx Virtex-4 Field Programmable Gate Array (FPGA) to provide self-repair using a novel approach called reconfigurable adaptive redundancy system (RARS). Reliability is often measured as probability of failure, frequency of failures, or in terms of availability, a probability derived from reliability and maintainability. View full text Microelectronics ReliabilityVolume 50, Issue 8, August 2010, Pages 1171–1180 Two effective methods to mitigate soft error effects in SRAM-based FPGAsAlireza Rohani , Hamid R. Previous techniques on FPGA SER estimation are based on time-consuming fault injection and simulation methods.In this paper, we present an analytical approach to estimate the failure rate of designs mapped into

The logic resources utilize a new function generator that can tolerate 100% of single faults in its configuration memory while it can generate all the k-input Boolean functions.