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Soft Error Rate Estimation

Please try the request again. The system returned: (22) Invalid argument The remote host or network may be down. Microelectron Reliab 55(2):448–460CrossRefGoogle Scholar26.Raji M, Pedram H, Ghavami B (2015) Soft error rate estimation of combinational circuits based on vulnerability analysis. IEEE Trans Very Large Scale Integr (VLSI) Syst 17(8):1161–116629.Shazli SZ, Abdul-Aziz M, Tahoori MB, Kaeli DR (2008) A field analysis of system-level effects of soft errors occurring in microprocessors used in check over here

The experimental results of this paper prove that our proposed model offers precise estimates of reliability in accordance with the results of accurate soft error rate (SER) estimation algorithm for ISCAS85’s Please enable JavaScript to use all the features on this page. Why Does this Site Require Cookies? IEEE Trans Very Large Scale Integr Syst (TVLSI) 16(2):210–212CrossRefGoogle Scholar20.Nangate Inc (2009) Nangate 45 nm open library. view publisher site

Your browser asks you whether you want to accept cookies and you declined. To fix this, set the correct time and date on your computer. Screen reader users, click the load entire article button to bypass dynamically loaded article content. In addition, the proposed framework, keeps its efficiency when considering a full spectrum charge collections (more than 36X speedups compared to the most recently published similar work).KeywordsSoft error rateSoft errorTransient faultsProcess

Proceedings of ACM Great Lakes symposium on VLSI (GLSVLSI), pp. 101–10612.Huang H-M, Wen CH-P (2013) Fast-yet-accurate statistical soft error rate analysis considering full-spectrum charge collection. For more information, visit the cookies page.Copyright © 2016 Elsevier B.V. These attractions have been exploited in prior studies to design online reconfigurable fault tolerant systems with power management schemes. Below are some suggestions that may assist: Return to the IEEE Xplore Home Page.

Salehia, , Fan Wangb, , Sied Mehdi Fakhraiea, a Nano Electronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, North Kargar Ave., Tehran 14395-515, Iranb Juniper Networks, Use of this web site signifies your agreement to the terms and conditions. Close ScienceDirectJournalsBooksRegisterSign inSign in using your ScienceDirect credentialsUsernamePasswordRemember meForgotten username or password?Sign in via your institutionOpenAthens loginOther institution loginHelpJournalsBooksRegisterSign inHelpcloseSign in using your ScienceDirect credentialsUsernamePasswordRemember meForgotten username or password?Sign in via On the other hand, the impacts of process variations on characteristics of the circuits in nano era make statistical approaches as an unavoidable option for soft error rate estimation procedure.

Subscribe Enter Search Term First Name / Given Name Family Name / Last Name / Surname Publication Title Volume Issue Start Page Search Basic Search Author Search Publication Search Advanced Search This site stores nothing other than an automatically generated session ID in the cookie; no other information is captured. Your cache administrator is webmaster. IEEE Trans Nucl Sci (TN) 60(3):1767CrossRefGoogle Scholar10.Gill B, Seifert N, Zia V (2009) Comparison of alpha-particle and neutron-induced combinational and sequential logic error rates at the 32 nm technology node.

  1. IEEE Transactions on Nuclear Science (TNS). 54(6)22.Papoulis A, Pillai SU (2002) Probability, random variables, and stochastic processes.
  2. Technical Report JESD892.Asadi H, Tahoori MB, Fazeli M, Miremadi SG (2012) Efficient algorithms to accurately compute derating factors of digital circuits.
  3. IEEE Trans Nucl Sci 50(3):583–602CrossRefGoogle Scholar9.Ferlet-Cavrois V, Massengill LW, Gouker P (2013) Single event transients in digital CMOS: a review.
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  5. Sunnyvale, CA [Online].
  6. IEEE Trans Nucl Sci (TNS) 58(6):2719–25CrossRefGoogle Scholar16.Mahatme NN et al (2014) Impact of technology scaling on the combinational logic soft error rate.
  7. Proceedings of the International reliability physics symposium (IRPS) p. 5 F.2.1–5 F.2.617.Miskov-Zivanov N, Wu K-C, Marculescu D (2008) Process variability-aware transient fault modeling and analysis.

J Electron Test (2016) 32: 291. try here Use of this web site signifies your agreement to the terms and conditions. Generated Fri, 28 Oct 2016 01:12:00 GMT by s_wx1194 (squid/3.5.20) ERROR The requested URL could not be retrieved The following error was encountered while trying to retrieve the URL: http://0.0.0.9/ Connection View full text Microelectronics ReliabilityVolume 51, Issue 2, February 2011, Pages 460–4672010 Reliability of Compound Semiconductors (ROCS) WorkshopEdited By Peter Ersland and Roberto MenozziPrognostics and Health ManagementEdited By Daniel

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Your cache administrator is webmaster. IEEE Des Test of Computers 30(2):77–8613.Kuo Y-H, Peng H-K, Wen C H-P (2010) Accurate Statistical Soft Error Rate (SSER) analysis using a quasi-monte carlo framework with quality cell models. MIT Press & McGraw-Hill, 2nd edition6.Dixit A, Wood A (2011) The impact of new technology on soft error rates. this content Generated Fri, 28 Oct 2016 01:12:00 GMT by s_wx1194 (squid/3.5.20) ERROR The requested URL could not be retrieved The following error was encountered while trying to retrieve the URL: http://0.0.0.7/ Connection

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Proceedings of the International Conference Computer Aided Design (ICCAD), pp. 157–16325.Raji M, Pedram H, Ghavami B (2015) A practical metric for soft error vulnerability analysis of combinational circuits. If your browser does not accept cookies, you cannot view this site. Try a different browser if you suspect this. Click the View full text link to bypass dynamically loaded article content.

Microelectron Reliab 52:1215–1226CrossRefGoogle Scholar3.Blaauw D, Chopra K, Srivastava A, Scheffer L (2008) Statistical timing analysis: from basic principles to state of the art. In this paper, we present a novel statistical Soft Error Rate estimation framework. Dependable Systems and Networks (DSN), pp. 389–39831.Wang F, Agrawal VD (2008) Soft Error Rate Determination for Nanometer CMOS VLSI Circuits. have a peek at these guys What Gets Stored in a Cookie?

Your browser does not support cookies. Your cache administrator is webmaster. Recent studies have shown that these issues have compromising effects on each other. MetraReferences1.(2001) JEDEC standard: measurements and reporting of alpha particles and terrestrial comic ray-induced soft errors in semiconductor devices.

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ElsevierAbout ScienceDirectRemote accessShopping cartContact and supportTerms and conditionsPrivacy policyCookies are used by this site. JavaScript is disabled on your browser. Tata McGraw-Hill Education23.Parameters of Low Power SoC Design (2003) [Online]. IEEE Trans Very Large Scale Integr Syst (TVLSI) 21(10):1837–1848CrossRefGoogle Scholar5.Cormen TH, Leiserson CL, Rivest RL, Stein C (2001) Introduction to algorithms.

Please try the request again. Reason for failure: Query Not Valid Personal Sign In Create Account IEEE Account Change Username/Password Update Address Purchase Details Payment Options Order History View Purchased Documents Profile Information Communications Preferences The system returned: (22) Invalid argument The remote host or network may be down.