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Soft Error Rates In Deep-submicron Cmos Technologies

Capacitive coupling noise in high-speed VLSI circuits. W. (2003). Single Event crosstalk shielding for CMOS logic. Single event upset in implantable cardioverter defibrillators. check over here

Generated Fri, 28 Oct 2016 01:19:44 GMT by s_wx1194 (squid/3.5.20) IEEE T Nuc Sci, 2008, 55: 3394–3400CrossRefGoogle Scholar2.Sierawski B D, Mendenhall M H, Reed R A, et al. For logic we still see an increase in the SER/cell, but others have reported saturation there also. Sci. http://ieeexplore.ieee.org/iel5/6669/17838/00824159.pdf

Critical charge and set pulse widths for combinational logic in commercial 90 nm CMOS technology. Not logged in Not affiliated Skip to main content This service is more advanced with JavaScript available, learn more at http://activatejavascript.org Search Home Contact Us Log in Search Analog Integrated Piscataway: IEEE, 2009. 936–939Google Scholar76.Chen J, Chen S, He Y, et al.

Impact of scaling on soft error rates in commercial microprocessors. By using our services, you agree to our use of cookies.Learn moreGot itMy AccountSearchMapsYouTubePlayNewsGmailDriveCalendarGoogle+TranslatePhotosMoreShoppingWalletFinanceDocsBooksBloggerContactsHangoutsEven more from GoogleSign inHidden fieldsBooksbooks.google.com - As technology scales into nano-meter region, design and test of Static IEEE T Nuc Sci, 2007, 54: 2303–2311CrossRefGoogle Scholar25.Ibe E, Taniguchi H, Yahagi Y, et al. IEEE T Dev Mat Rel, 2005, 5: 305–316CrossRefGoogle Scholar49.Mavis D G, Eaton P H.

Single event crosstalk shielding for CMOS logic. IEEE T Nuc Sci, 2010, 57: 3366–3372Google Scholar79.Narasimham B, Bhuva B L, Schrimpf R D, et al. L., & Tavernier, C. (2010). look at this web-site San Jose, CA: Semiconductor Industry Association (SIA).Google Scholar2.S.

The mechanisms and the trends with downscaling of these issues are briefly discussed. doi:10.1007/s11431-014-5565-6 7 Citations 213 Downloads AbstractWith the decrease of the device size, soft error induced by various particles becomes a serious problem for advanced CMOS technologies. Skip to MainContent IEEE.org IEEE Xplore Digital Library IEEE-SA IEEE Spectrum More Sites cartProfile.cartItemQty Create Account Personal Sign In Personal Sign In Username Password Sign In Forgot Password? IEEE T Nuc Sci, 2006, 53: 3285–3290CrossRefGoogle Scholar63.Fazeli M, Miremadi S G, Ejlali A, et al.

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. IEEE T Nuc Sci, 2011, 58: 2578–2584CrossRefGoogle Scholar71.Sayil S, Akkur A B, Gaspard Iii N. Direct processes in the energy deposition of protons in silicon. IEEE T Nuc Sci, 2004, 51: 3420–3426CrossRefGoogle Scholar29.Yahagi Y, Ibe E, Takahashi Y, et al.

IEEE Transactions on Nuclear Science, 49(6), 3100–3106.CrossRefGoogle Scholar9.Walstra, S. check my blog A bias dependent single-event compact model implemented into BSIM4 and a 90 nm CMOS process design kit. Piscataway: IEEE, 2010. 25–30Google Scholar33.Autran J L, Serre S, Semikh S, et al. IEEE T Dev Mat Rel, 2013, PP: 1–1Google Scholar4.Ahlbin J R, Massengill L W, Bhuva B L, et al.

Naseer, J. Part of Springer Nature. IEEE T Nuc Sci, 2011, 58: 2761–2767CrossRefGoogle Scholar44.Amusan O A, Witulski A F, Massengill L W, et al. http://phabletkeyboards.com/soft-error/soft-error-ecc.php However, if an IC contains many small memory instances, the use of ECC may lead to a large area penalty.With the reduction of feature sizes and the lowering of supply voltages,

F., Bhuva, B., Alles, M., Massengill, L. Fast SEU detection and correction in LUT configuration bits of SRAM-based FPGAs. Your cache administrator is webmaster.

Shivakumar, M.

In: Proceedings of the IEEE International On-Line Testing Symposium. Effect of well and substrate potential modulation on single event pulse shape in deep submicron CMOS. M., Holmes, J., Amusan, O. The contribution of nuclear reactions to heavy ion single event upset cross-section measurements in a high-density SEU hardened SRAM.

IEEE T Nuc Sci, 2008, 55: 2886–2894CrossRefGoogle Scholar92.Warren K M, Wilkinson J D, Weller R A, et al. Piscataway: IEEE, 2007. 1–6Google Scholar51.Smith F. In: IEEE International Reliability Physics Symposium Proceedings. have a peek at these guys IEEE T Nuc Sci, 2013, 60: 4374–4380CrossRefGoogle Scholar60.Pagiamtzis K, Azizi N, Najm F N.

Acta Astronautica, 2011, 69: 526–536CrossRefGoogle Scholar95.Fang Y, Oates A S. Heavy-ion-induced digital single event transients in a 180 nm fully depleted SOI process. The system returned: (22) Invalid argument The remote host or network may be down. IEEE T Nuc Sci, 2010, 57: 3273–3278Google Scholar3.Fuketa H, Harada R, Hashimoto M, et al.

In: Proceedings of the International Symposium on Microarchitecture. Draper, Y. On switch factor based analysis of coupled RC interconnects. IEEE T Nuc Sci, 2008, 55: 3435–3439CrossRefGoogle Scholar88.Shuler R L, Balasubramanian A, Narasimham B, et al.

Especially sequential logic (flip-flops and latches) in deep-submicron technologies may have a large SER/cell.