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Soft Error Rates In Deep-submicron Cmos Technologies

Capacitive coupling noise in high-speed VLSI circuits. W. (2003). Single Event crosstalk shielding for CMOS logic. Single event upset in implantable cardioverter defibrillators. check over here

Generated Fri, 28 Oct 2016 01:19:44 GMT by s_wx1194 (squid/3.5.20) IEEE T Nuc Sci, 2008, 55: 3394–3400CrossRefGoogle Scholar2.Sierawski B D, Mendenhall M H, Reed R A, et al. For logic we still see an increase in the SER/cell, but others have reported saturation there also. Sci. http://ieeexplore.ieee.org/iel5/6669/17838/00824159.pdf

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Impact of scaling on soft error rates in commercial microprocessors. By using our services, you agree to our use of cookies.Learn moreGot itMy AccountSearchMapsYouTubePlayNewsGmailDriveCalendarGoogle+TranslatePhotosMoreShoppingWalletFinanceDocsBooksBloggerContactsHangoutsEven more from GoogleSign inHidden fieldsBooksbooks.google.com - As technology scales into nano-meter region, design and test of Static IEEE T Nuc Sci, 2007, 54: 2303–2311CrossRefGoogle Scholar25.Ibe E, Taniguchi H, Yahagi Y, et al. IEEE T Dev Mat Rel, 2005, 5: 305–316CrossRefGoogle Scholar49.Mavis D G, Eaton P H.

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The mechanisms and the trends with downscaling of these issues are briefly discussed. doi:10.1007/s11431-014-5565-6 7 Citations 213 Downloads AbstractWith the decrease of the device size, soft error induced by various particles becomes a serious problem for advanced CMOS technologies. Skip to MainContent IEEE.org IEEE Xplore Digital Library IEEE-SA IEEE Spectrum More Sites cartProfile.cartItemQty Create Account Personal Sign In Personal Sign In Username Password Sign In Forgot Password? IEEE T Nuc Sci, 2006, 53: 3285–3290CrossRefGoogle Scholar63.Fazeli M, Miremadi S G, Ejlali A, et al.

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Especially sequential logic (flip-flops and latches) in deep-submicron technologies may have a large SER/cell.