Customer Support ProQuest.com Dissertations & Theses - Gradworks The world's most comprehensive collection of dissertations and theses. Violators will lose library privileges, face disciplinary actions and may be prosecuted. The asynchronous circuit Null Convention Logic (NCL) is implemented in FPGA to analyze the discipline of FPGA implementation asynchronous circuits. Errors may be caused by a defect, usually understood either to be a mistake in design or construction, or a broken component. http://ieeexplore.ieee.org/iel5/6036122/6037383/06037416.pdf
Generated Fri, 28 Oct 2016 01:13:31 GMT by s_hp90 (squid/3.5.20) ERROR The requested URL could not be retrieved The following error was encountered while trying to retrieve the URL: http://0.0.0.9/ Connection This digital logic design is contrasted with a synchronous circuit which operates according to clock timing signal. Ideally, the input to each storage element has reached its final value before the next clock occurs, so the behaviour of the whole circuit can be predicted exactly. We introduce NULL Convention Logic in relation to Boolean logic as a four value logic, and as a three value logic and finally as two value logic quite different from traditional
In philosophy, the study of logic is applied in most major areas: metaphysics, ontology, epistemology, and ethics. A soft error is also a signal or datum which is wrong, but is not assumed to imply such a mistake or breakage. Other uses and excessive downloading are strictly prohibited. https://www.researchgate.net/publication/252004289_Soft_error_in_FPGA-implemented_asynchronous_circuits Although carefully collected, accuracy cannot be guaranteed.
Of the nearly 4 million graduate works included in the database, ProQuest offers more than 2.5 million in full text formats. This paper addresses the issue of soft errors in Quasi Delay-Insensitive (QDI) FPGA (Field-Programmable Gate Array). Fabula+1 more author ...R. All rights reserved.
State logic enables users to model the application they are trying to control by using a hierarchy that consists of Tasks, subdivided by States which are described by Statements. 'Tasks' are check my blog Please try the request again. The research on soft error injection in FPGA routing system and soft error rate estimation will be done in the future.AdviserWeidong Kuang SchoolTHE UNIVERSITY OF TEXAS - PAN AMERICAN Source Read our cookies policy to learn more.OkorDiscover by subject areaRecruit researchersJoin for freeLog in EmailPasswordForgot password?Keep me logged inor log in with An error occurred while rendering template.
We describe and validate an end-to-end model that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs. Our result emphasizes that computer system designers must address the risks of soft errors in logic circuits for future designs.Conference Paper · Feb 2002 Premkishore ShivakumarMichael KistlerStephen W. Additional materials are deposited and patterned to form interconnections between semiconductor devices. this content After observing a soft error, there is no implication that the system is any less reliable than before.
morefromWikipedia State logic A state logic control system is a programming method created for PLCs. If not, you will have the option to purchase one, and access a 24 page preview for free (if available). The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration,
rgreq-f2079cf0b0d29b812ed43f5c4d09591d false SIGN IN SIGN UP Soft Error Tolerant Asynchronous Circuits Based on Dual Redundant Four State Logic Authors: Werner Friesenbichler Andreas Steininger Published in: ·Proceeding DSD '09 Proceedings of Did you know your Organization can subscribe to the ACM Digital Library? Institutional Sign In By Topic Aerospace Bioengineering Communication, Networking & Broadcasting Components, Circuits, Devices & Systems Computing & Processing Engineered Materials, Dielectrics & Plasmas Engineering Profession Fields, Waves & Electromagnetics General Please try the request again.
Your cache administrator is webmaster. See all ›10 ReferencesShare Facebook Twitter Google+ LinkedIn Reddit Request full-text Soft error in FPGA-implemented asynchronous circuitsArticle · April 2011 with 86 ReadsDOI: 10.1109/SPL.2011.5782652 1st Weidong Kuang2nd Yu BaiAbstractIn this paper, we investigate the mechanism Based on the behavior of soft error transmission in FPGA-implement circuit, the detection circuit is proposed to detect soft error. have a peek at these guys Full-text · Conference Paper · Oct 2001 F.
morefromWikipedia Tools and Resources Save to Binder Export Formats: BibTeX EndNote ACMRef Share: | Author Tags soft error, fpga, asynchronous circuit, detection circuit Contact Us | Switch to single page view Please try the request again. The conclusion are drawn that asynchronous circuit are much easier to detect soft error than synchronous circuits. A soft error is also a signal or datum which is wrong, but is not assumed to imply such a mistake or breakage.
Copyright © 2016 ACM, Inc. The proton radiation ground test has confirmed the results achieved by fault injection. morefromWikipedia Integrated circuit An integrated circuit or monolithic integrated circuit (also referred to as IC, chip, or microchip) is an electronic circuit manufactured by lithography, or the patterned diffusion of trace The system returned: (22) Invalid argument The remote host or network may be down.