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Soft Error Tutorial

degree in physics from the Technical University of Vienna, Austria, in 1993. A consequence of rapid technology scaling is that transistors become more susceptible to soft errors, caused by charge-carrying energy particles; leading to system failures due to data corruption. He has held several consulting positions, and served on the organizing and program committees of several IEEE and ACM sponsored conferences. Terms of Usage Privacy Policy Code of Ethics Contact Us Useful downloads: Adobe Reader QuickTime Windows Media Player Real Player Did you know the ACM DL App is http://phabletkeyboards.com/soft-error/soft-error-ecc.php

Prof. His X-Compact technique for test compression has been used by more than 40 Intel products including microprocessors, chipsets, and communications chips, and is supported by major CAD tools. For a researcher, the tutorial will be a valuable one-stop-shop to acquire knowledge of and analyze seminal research work in the field of soft error mitigation, at each of the design layers. The tutorial will cater to a wide audience comprising of both (i) researchers specializing in embedded and high performance computing, and (ii) system designers, architects, and programmers from the industry.

in Electrical Engineering from Stanford University. Tutorial IEEE Computer Society Test Technology Technical Council (TTTC) Test Technology Educational Program (TTEP) 2007 http://tab.computer.org/tttc/teg/ttep Soft Errors: Technology Trends, System Effects, and Protection Techniques Subhasish Mitra (Stanford University) Pia Sanda Copyright © 2016 ACM, Inc.

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  3. This tutorial will discuss the impact of technology scaling on soft error rates, circuit-level modeling of soft errors, architectural impact of soft errors, challenges associated with evaluation of run-time behaviors of
  4. She was a Manager in the VLSI Design Area, IBM T.
  5. The industry, realizing this urgency to ensure application reliability, have sacrificed power and hardware overheads to protect the data stored (even temporarily) in the processor.

His most recent honors include the IEEE Circuits and Systems Society Donald O. Pederson Award, a Best Paper Award nomination at the Design Automation Conference, a Divisional Recognition Award from the Intel “for a Breakthrough Soft Error Protection Technology,” a Best Paper Award at For instance, the L1, L2 cache and register files of NVIDIA's Tesla Personal Supercomputing GPUs are ECC protected; and the local memories in each of the 8 processors of the IBM Please try the request again.

Reiley Jeyapaul    BrowseHome Members Research Publications Sponsors Resources Login Copyright © Compiler Microarchitecture Lab Designed by: Cheap Web Hosting | Thanks to Highest CD Rates, Las Vegas Condos and Registry The system returned: (22) Invalid argument The remote host or network may be down. Seifert joined the Alpha Development Group (DEC/Compaq/HP) where he worked in the fields of device physics, device reliability, and digital design. Power5 case study for on-line checking.

Norbert Seifert. 60 mins: Logic and Architectural soft error protection techniques: Built-In Soft Error Resilience, Soft Error Correcting Combinational Logic, ECC, Concurrent Error Detection, Parity Prediction, Multi-threading, Software Implemented Hardware Fault He is a frequent reviewer for IEEE Transaction on Device and Materials Reliability (TDMR) and is a co-editor of the Special Issue on Soft Errors and Data Integrity in Terrestrial Computer She has been engaged in designing high-performance circuits for microprocessors and has recently explored new avenues for test and improved semiconductor manufacturability, such as the new PICA measurement technique. Speakers Prof.

Seifert has conducted research in a wide range of physics topics, from charge transfer processes in atomic collisions as a postdoctoral associate at North Carolina State University, to computational fluid dynamics http://www.ewh.ieee.org/r6/scv/rl/articles/Soft%20Error%20mitigation.pdf This has accelerated our dependence on computation devices for a wide range of applications from embedded systems to manageable supercomputers. From an industry perspective, modifications to an existing design need to be weighed against possible gains, and we understand that such a decision is not taken lightly. thesis focuses on radiation-induced defect formation and diffusion in wide band gap ionic crystals.

Get Help About IEEE Xplore Feedback Technical Support Resources and Help Terms of Use What Can I Access? have a peek at these guys Stringent data integrity and availability requirements of enterprise computing and networking applications demand special attention to soft errors in sequential elements and combinational logic. Generated Fri, 28 Oct 2016 06:15:10 GMT by s_sg2 (squid/3.5.20) Use of this web site signifies your agreement to the terms and conditions.

This part will be covered by Prof. Generated Fri, 28 Oct 2016 06:15:10 GMT by s_sg2 (squid/3.5.20) ERROR The requested URL could not be retrieved The following error was encountered while trying to retrieve the URL: Connection The tutorial is shaped to showcase some very efficient design methodologies at both the software, and hardware layers, that could prove to be key design decisions targeted towards improving the reliability of future check over here He received Ph.D.

She began her career at IBM in imaging science. Watson Research Center, Yorktown Heights, NY. Mitra is a 2006 Terman Fellow at Stanford.

In silicon technology, she designed and built 0.1-m channel length CMOS FET’s using phase shift lithography and contributed to the device and cell design for the 256-Mb DRAM.

Your cache administrator is webmaster. Dr. Subscribe Enter Search Term First Name / Given Name Family Name / Last Name / Surname Publication Title Volume Issue Start Page Search Basic Search Author Search Publication Search Advanced Search Generated Fri, 28 Oct 2016 06:15:10 GMT by s_sg2 (squid/3.5.20) ERROR The requested URL could not be retrieved The following error was encountered while trying to retrieve the URL: Connection

Dr. In this tutorial, we will discuss various soft-error mitigation techniques at all design layers, with a particular focus on those at the compiler and microarchitecture layers. We elaborate on key works that had been instrumental in providing orthogonal dimensions of approaches to solving the problem of computation reliability. this content Kyoungwoo Lee Dr.

Register now for a free account in order to: Sign in to various IEEE sites with a single account Manage your membership Get member discounts Personalize your experience Manage your profile Please try the request again. Please try the request again. Norbert Seifert holds an M.S.

He is currently a Staff Reliability and Design Engineer with Intel Corporation in Hillsboro, Oregon, where he is responsible for all aspects of developing accurate SER models and a coherent chip-level Subhasish Mitra.